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CS42432 108 dB, 192 kHz 4-In, 6-Out TDM CODEC
FEATURES
Four 24-bit A/D, Six 24-bit D/A Converters ADC Dynamic Range - 105 dB Differential - 102 dB Single-Ended DAC Dynamic Range - 108 dB Differential - 105 dB Single-Ended ADC/DAC THD+N - -98 dB Differential - -95 dB Single-Ended Compatible with Industry-Standard Time Division Multiplexed (TDM) Serial Interface DAC Sampling Rates up to 192 kHz ADC Sampling Rates up to 96 kHz Programmable ADC High-Pass Filter for DC Offset Calibration Logarithmic Digital Volume Control Hardware Mode or Software IC(R) & SPITM Supports Logic Levels Between 5 V and 1.8 V
GENERAL DESCRIPTION
The CS42432 CODEC provides four multi-bit analog-todigital and six multi-bit digital-to-analog delta-sigma converters. The CODEC is capable of operation with either differential or single-ended inputs and outputs, in a 52-pin MQFP package.
Four fully differential, or single-ended, inputs are avail-
able on stereo ADC1 and ADC2. Digital volume control is provided for each ADC channel, with selectable overflow detection. All six DAC channels provide digital volume control and can operate with differential or single-ended outputs. An auxiliary serial input is available for an additional two channels of PCM data. The CS42432 is available in a 52-pin MQFP package in Commercial (-10 to +70) and Automotive (-40 to +105) grades. The CDB42432 Customer Demonstration board is also available for device evaluation and implementation suggestions. Please refer to "Ordering Information" on page 58 for complete ordering information. The CS42432 is ideal for audio systems requiring wide dynamic range, negligible distortion and low noise, such as A/V receivers, DVD receivers, and automotive audio systems.
Control Port & Serial Audio Port Supply = 1.8 V to 5 V
Digital Supply = 3.3 V
Analog Supply = 3.3 V to 5 V
Level Translator
Hardware Mode or I2C/SPI Software Mode Control Data
Register Configuration
Internal Voltage Reference
Reset
Level Translator
TDM Serial Audio Input Auxilliary Serial Audio Input Input Master Clock TDM Serial Audio Output
Volume Controls TDM Serial Interface
Digital Filters
Modulators
Multibit DAC1-3 and Analog Filters
6 6
Differential or Single-Ended Outputs
High Pass Filter High Pass Filter
Digital Filters Digital Filters
Multibit Oversampling ADC1 Multibit Oversampling ADC2
2 2
Differential or Single-Ended Analog Inputs
2 2
http://www.cirrus.com
Copyright (c) Cirrus Logic, Inc. 2006 (All Rights Reserved)
AUGUST '06 DS673F1
CS42432
TABLE OF CONTENTS
1. PIN DESCRIPTIONS - SOFTWARE MODE ........................................................................................... 6 1.1 Digital I/O Pin Characteristics ........................................................................................................... 8 2. PIN DESCRIPTIONS - HARDWARE MODE .......................................................................................... 9 3. TYPICAL CONNECTION DIAGRAMS ................................................................................................. 11 4. CHARACTERISTICS AND SPECIFICATIONS .................................................................................... 13 RECOMMENDED OPERATING CONDITIONS ................................................................................... 13 ABSOLUTE MAXIMUM RATINGS ....................................................................................................... 13 ANALOG INPUT CHARACTERISTICS (COMMERCIAL) .................................................................... 14 ANALOG INPUT CHARACTERISTICS (AUTOMOTIVE) ..................................................................... 15 ADC DIGITAL FILTER CHARACTERISTICS ....................................................................................... 16 ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL) ................................................................ 17 ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE) ................................................................. 18 COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE .............................. 20 SWITCHING SPECIFICATIONS - ADC/DAC PORT ............................................................................ 21 SWITCHING CHARACTERISTICS - AUX PORT ................................................................................. 22 SWITCHING SPECIFICATIONS - CONTROL PORT - IC MODE ....................................................... 23 SWITCHING SPECIFICATIONS - CONTROL PORT - SPI FORMAT ................................................. 24 DC ELECTRICAL CHARACTERISTICS .............................................................................................. 25 DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS ..................................................... 25 5. APPLICATIONS ................................................................................................................................... 26 5.1 Overview ......................................................................................................................................... 26 5.2 Analog Inputs .................................................................................................................................. 27 5.2.1 Line-Level Inputs ................................................................................................................... 27 5.2.1.1 Hardware Mode ......................................................................................................... 27 5.2.1.2 Software Mode ........................................................................................................... 27 5.2.2 High-Pass Filter and DC Offset Calibration ........................................................................... 27 5.2.2.1 Hardware Mode ......................................................................................................... 28 5.2.2.2 Software Mode ........................................................................................................... 28 5.3 Analog Outputs ............................................................................................................................... 28 5.3.1 Initialization ............................................................................................................................ 28 5.3.2 Line-Level Outputs and Filtering ........................................................................................... 28 5.3.3 Digital Volume Control ........................................................................................................... 30 5.3.3.1 Hardware Mode ......................................................................................................... 30 5.3.3.2 Software Mode ........................................................................................................... 30 5.3.4 De-Emphasis Filter ................................................................................................................ 30 5.4 System Clocking ............................................................................................................................. 31 5.4.1 Hardware Mode ..................................................................................................................... 31 5.4.2 Software Mode ...................................................................................................................... 31 5.5 CODEC Digital Interface ................................................................................................................. 31 5.5.1 TDM ....................................................................................................................................... 31 5.5.2 I/O Channel Allocation ........................................................................................................... 32 5.6 AUX Port Digital Interface Formats ................................................................................................ 32 5.6.1 Hardware Mode ..................................................................................................................... 32 5.6.2 Software Mode ...................................................................................................................... 32 5.6.3 IS .......................................................................................................................................... 32 5.6.4 Left-Justified .......................................................................................................................... 33 5.7 Control Port Description and Timing ............................................................................................... 33 5.7.1 SPI Mode ............................................................................................................................... 33 5.7.2 IC Mode ................................................................................................................................ 34 5.8 Recommended Power-Up Sequence ............................................................................................. 35 5.8.1 Hardware Mode ..................................................................................................................... 35 5.8.2 Software Mode ...................................................................................................................... 36 2 DS673F1
CS42432
5.9 Reset and Power-Up ...................................................................................................................... 36 5.10 Power Supply, Grounding, and PCB Layout ................................................................................ 36 6. REGISTER QUICK REFERENCE ........................................................................................................ 37 7. REGISTER DESCRIPTION .................................................................................................................. 39 7.1 Memory Address Pointer (MAP) ..................................................................................................... 39 7.1.1 Increment (INCR) .................................................................................................................. 39 7.1.2 Memory Address Pointer (MAP[6:0]) ..................................................................................... 39 7.2 Chip I.D. and Revision Register (Address 01h) (Read Only) ......................................................... 39 7.2.1 Chip I.D. (CHIP_ID[3:0]) ........................................................................................................ 39 7.2.2 Chip Revision (REV_ID[3:0]) ................................................................................................. 39 7.3 Power Control (Address 02h) ......................................................................................................... 40 7.3.1 Power Down ADC Pairs (PDN_ADCX) ................................................................................. 40 7.3.2 Power Down DAC Pairs (PDN_DACX) ................................................................................. 40 7.3.3 Power Down (PDN) ............................................................................................................... 40 7.4 Functional Mode (Address 03h) ..................................................................................................... 41 7.4.1 MCLK Frequency (MFREQ[2:0]) ........................................................................................... 41 7.5 Miscellaneous Control (Address 04h) ............................................................................................. 41 7.5.1 Freeze Controls (FREEZE) ................................................................................................... 41 7.5.2 Auxiliary Digital Interface Format (AUX_DIF) ........................................................................ 41 7.6 ADC Control & DAC De-Emphasis (Address 05h) ......................................................................... 42 7.6.1 ADC1-2 High-Pass Filter Freeze (ADC1-2_HPF FREEZE) .................................................. 42 7.6.2 DAC De-Emphasis Control (DAC_DEM) ............................................................................... 42 7.6.3 ADC1 Single-Ended Mode (ADC1 SINGLE) ......................................................................... 42 7.6.4 ADC2 Single-Ended Mode (ADC2 SINGLE) ......................................................................... 43 7.7 Transition Control (Address 06h) .................................................................................................... 43 7.7.1 Single Volume Control (DAC_SNGVOL, ADC_SNGVOL) .................................................... 43 7.7.2 Soft Ramp and Zero Cross Control (ADC_SZC[1:0], DAC_SZC[1:0]) .................................. 43 7.7.3 Auto-Mute (AMUTE) .............................................................................................................. 44 7.7.4 Mute ADC Serial Port (MUTE ADC_SP) ............................................................................... 44 7.8 DAC Channel Mute (Address 07h) ................................................................................................. 44 7.8.1 Independent Channel Mute (AOUTX_MUTE) ....................................................................... 44 7.9 AOUTX Volume Control (Addresses 08h-0D) ............................................................................ 45 7.9.1 Volume Control (AOUTX_VOL[7:0]) ...................................................................................... 45 7.10 DAC Channel Invert (Address 10h) .............................................................................................. 45 7.10.1 Invert Signal Polarity (INV_AOUTX) .................................................................................... 45 7.11 AINX Volume Control (Address 11h-14h) ..................................................................................... 45 7.11.1 AINX Volume Control (AINX_VOL[7:0]) .............................................................................. 45 7.12 ADC Channel Invert (Address 17h) .............................................................................................. 46 7.12.1 Invert Signal Polarity (INV_AINX) ........................................................................................ 46 7.13 Status (Address 19h) (Read Only) ............................................................................................... 46 7.13.1 CLOCK ERROR (CLK ERROR) .......................................................................................... 46 7.13.2 ADC Overflow (ADCX_OVFL) ............................................................................................. 46 7.14 Status Mask (Address 1Ah) .......................................................................................................... 47 8. EXTERNAL FILTERS ........................................................................................................................... 48 8.1 ADC Input Filter .............................................................................................................................. 48 8.1.1 Passive Input Filter ................................................................................................................ 49 8.1.2 Passive Input Filter w/Attenuation ......................................................................................... 49 8.2 DAC Output Filter ........................................................................................................................... 50 9. ADC FILTER PLOTS ............................................................................................................................ 51 10. DAC FILTER PLOTS .......................................................................................................................... 53 11. PARAMETER DEFINITIONS .............................................................................................................. 55 12. REFERENCES .................................................................................................................................... 56 13. PACKAGE INFORMATION ................................................................................................................ 57 13.1 Thermal Characteristics ............................................................................................................... 57 DS673F1 3
CS42432
14. ORDERING INFORMATION .............................................................................................................. 58 15. REVISION HISTORY .......................................................................................................................... 58
LIST OF FIGURES
Figure 1.Typical Connection Diagram (Software Mode) ........................................................................... 11 Figure 2.Typical Connection Diagram (Hardware Mode) .......................................................................... 12 Figure 3.Output Test Load ........................................................................................................................ 19 Figure 4.Maximum Loading ....................................................................................................................... 19 Figure 5.TDM Serial Audio Interface Timing ............................................................................................. 21 Figure 6.Serial Audio Interface Slave Mode Timing .................................................................................. 22 Figure 7.Control Port Timing - IC Format ................................................................................................. 23 Figure 8.Control Port Timing - SPI Format ................................................................................................ 24 Figure 9.Full-Scale Input ........................................................................................................................... 27 Figure 10.Audio Output Initialization Flow Chart ....................................................................................... 29 Figure 11.Full-Scale Output ...................................................................................................................... 30 Figure 12.De-Emphasis Curve .................................................................................................................. 31 Figure 13.TDM Serial Audio Format ......................................................................................................... 32 Figure 14.AUX IS Format ......................................................................................................................... 32 Figure 15.AUX Left-Justified Format ......................................................................................................... 33 Figure 16.Control Port Timing in SPI Mode .............................................................................................. 34 Figure 17.Control Port Timing, IC Write ................................................................................................... 34 Figure 18.Control Port Timing, IC Read ................................................................................................... 35 Figure 19.Single-to-Differential Active Input Filter ..................................................................................... 48 Figure 20.Single-Ended Active Input Filter ................................................................................................ 48 Figure 21.Passive Input Filter ................................................................................................................... 49 Figure 22.Passive Input Filter w/Attenuation ............................................................................................. 49 Figure 23.Active Analog Output Filter ....................................................................................................... 50 Figure 24.Passive Analog Output Filter .................................................................................................... 50 Figure 25.SSM Stopband Rejection .......................................................................................................... 51 Figure 26.SSM Transition Band ................................................................................................................ 51 Figure 27.SSM Transition Band (Detail) ................................................................................................... 51 Figure 28.SSM Passband Ripple .............................................................................................................. 51 Figure 29.DSM Stopband Rejection .......................................................................................................... 51 Figure 30.DSM Transition Band ................................................................................................................ 51 Figure 31.DSM Transition Band (Detail) ................................................................................................... 52 Figure 32.DSM Passband Ripple .............................................................................................................. 52 Figure 33.SSM Stopband Rejection .......................................................................................................... 53 Figure 34.SSM Transition Band ................................................................................................................ 53 Figure 35.SSM Transition Band (detail) .................................................................................................... 53 Figure 36.SSM Passband Ripple .............................................................................................................. 53 Figure 37.DSM Stopband Rejection .......................................................................................................... 53 Figure 38.DSM Transition Band ................................................................................................................ 53 Figure 39.DSM Transition Band (detail) .................................................................................................... 54 Figure 40.DSM Passband Ripple .............................................................................................................. 54 Figure 41.QSM Stopband Rejection ......................................................................................................... 54 Figure 42.QSM Transition Band ................................................................................................................ 54 Figure 43.QSM Transition Band (detail) .................................................................................................... 54 Figure 44.QSM Passband Ripple .............................................................................................................. 54
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LIST OF TABLES
Table 1. I/O Power Rails ............................................................................................................................. 8 Table 2. Hardware Configurable Settings ................................................................................................. 26 Table 3. MCLK Frequency Settings .......................................................................................................... 31 Table 4. Serial Audio Interface Channel Allocations ................................................................................. 32 Table 5. MCLK Frequency Settings .......................................................................................................... 41 Table 6. Example AOUT Volume Settings ................................................................................................ 45 Table 7. Example AIN Volume Settings .................................................................................................... 46
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CS42432 1. PIN DESCRIPTIONS - SOFTWARE MODE
AGND FILT+ VA AIN4+ AIN4AIN3+ AIN3AIN2+ AIN2TSTN TSTN TSTN TSTN
52 51 50 49 48 47 46 45 44 43 42 41 40 SCL/CCLK SDA/CDOUT AD1/CDIN AD0/CS RST VLC FS VD DGND VLS SCLK MCLK ADC_SDOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 AUX_SCLK AUX_SDIN DGND AOUT1AOUT1+ DAC_SDIN AUX_LRCK AOUT2+ AOUT2AOUT3AOUT3+ AOUT4+ AOUT439 38 37 36 35 34 AIN1+ AIN1VA VQ AGND TSTO TSTO TSTO TSTO AOUT6AOUT6+ AOUT5+ AOUT5-
42432
33 32 31 30 29 28 27
Pin Name
SCL/CCLK SDA/CDOUT AD0/CS AD1/CDIN RST VLC FS VD DGND VLS SCLK MCLK ADC_SDOUT DAC_SDIN AUX_LRCK
#
1 2 3 4 5 6 7 8 9,18 10 11 12 13 14 15
Pin Description
Serial Control Port Clock (Input) - Serial clock for the control port interface. Serial Control Data I/O (Input/Output) - Input/Output for IC data. Output for SPI data. Address Bit [0]/ Chip Select (Input) - Chip address bit in IC Mode. Control signal used to select the chip in SPI Mode. Address Bit [1]/ SPI Data Input (Input) - Chip address bit in IC Mode. Input for SPI data. Reset (Input) - The device enters a low-power mode and all internal registers are reset to their default settings when low. Control Port Power (Input) - Determines the required signal level for the control port interface. See "Digital I/O Pin Characteristics" on page 8. Frame Sync (Input) - Signals the start of a new TDM frame in the TDM digital interface format. Digital Power (Input) - Positive power supply for the digital section. Digital Ground (Input) - Ground reference for the digital section. Serial Port Interface Power (Input) - Determines the required signal level for the serial port interfaces. See "Digital I/O Pin Characteristics" on page 8. Serial Clock (Input) - Serial clock for the serial audio interface. Input frequency must be 256 x Fs. Master Clock (Input) - Clock source for the delta-sigma modulators and digital filters. Serial Audio Data Output (Output) - TDM output for two's complement serial audio data. DAC Serial Audio Data Input (Input) - TDM Input for two's complement serial audio data. Auxiliary Left/Right Clock (Output) - Determines which channel, Left or Right, is currently active on the Auxiliary serial audio data line.
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AUX_SCLK AUX_SDIN AOUT1 +,AOUT2 +,AOUT3 +,AOUT4 +,AOUT5 +,AOUT6 +,TSTO TSTN AGND VQ VA 16 17 Auxiliary Serial Clock (Output) - Serial clock for the Auxiliary serial audio interface. Auxiliary Serial Input (Input) - The 42432 provides an additional serial input for two's complement serial audio data.
20,19 21,22 Differential Analog Output (Output) - The full-scale differential analog output level is specified in 24,23 the Analog Characteristics specification table. Each positive leg of the differential outputs may 25,26 also be used single-ended. 28,27 29,30 31,32 Test Out - These pins are outputs used for test purposes only. They must not be connected to any 33,34 external trace or other connection. 49,50 Test In - These pins are inputs used for test purposes only. They must be tied to ground for nor51,52 mal operation. 35,48 Analog Ground (Input) - Ground reference for the analog section. 36 Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage.
37,46 Analog Power (Input) - Positive power supply for the analog section. 39,38 Differential Analog Input (Input) - Signals are presented differentially to the delta41,40 sigma modulators. The full-scale input level is specified in the Analog Characteristics 43,42 45,44 specification table. 47 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
AIN1 +,AIN2 +,AIN3 +,AIN4 +,FILT+
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CS42432
1.1 Digital I/O Pin Characteristics
Various pins on the CS42432 are powered from separate power supply rails. The logic level for each input should adhere to the corresponding power rail and should not exceed the maximum ratings. Power Rail
VLC
Pin Name SW/(HW)
RST SCL/CCLK (TEST) SDA/CDOUT (TEST) AD0/CS (MFREQ) AD1/CDIN (TEST)
I/O
Input Input Input/ Output Input Input Input Input Input Input/ Output Input Output Output Input
Driver
1.8 V - 5.0 V, CMOS/Open Drain -
Receiver
1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS, with Hysteresis 1.8 V - 5.0 V, CMOS, with Hysteresis 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS
VLS
MCLK LRCK SCLK ADC_SDOUT2 DAC_SDIN AUX_LRCK AUX_SCLK AUX_SDIN
1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS -
Table 1. I/O Power Rails
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CS42432 2. PIN DESCRIPTIONS - HARDWARE MODE
AGND AIN4+ AIN3+ VA AIN2+ AIN2FILT+ TSTN TSTN TSTN TSTN AIN4AIN3-
52 51 50 49 48 47 46 45 44 43 42 41 40 TEST TEST MFREQ TEST RST VLC FS VD DGND VLS SCLK MCLK ADC_SDOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 AOUT1AOUT2AOUT3AOUT1+ DAC_SDIN AUX_SDIN AUX_LRCK AUX_SCLK AOUT2+ AOUT4+ AOUT4DGND AOUT3+ 39 38 37 36 35 34 33 32 31 30 29 28 27 AIN1+ AIN1VA VQ AGND TSTO TSTO TSTO TSTO AOUT6AOUT6+ AOUT5+ AOUT5-
42432
Pin Name
SCL/CCLK SDA/CDOUT AD0/CS AD1/CDIN RST VLC FS VD DGND VLS SCLK MCLK ADC_SDOUT DAC_SDIN AUX_LRCK AUX_SCLK
#
1 2 3 4 5 6 7 8 9,18 10 11 12 13 14 15 16
Pin Description
Serial Control Port Clock (Input) - Serial clock for the control port interface. Serial Control Data I/O (Input/Output) - Input/Output for IC data. Output for SPI data. Address Bit [0]/ Chip Select (Input) - Chip address bit in IC Mode. Control signal used to select the chip in SPI Mode. Address Bit [1]/ SPI Data Input (Input) - Chip address bit in IC Mode. Input for SPI data. Reset (Input) - The device enters a low-power mode and all internal registers are reset to their default settings when low. Control Port Power (Input) - Determines the required signal level for the control port interface. See "Digital I/O Pin Characteristics" on page 8. Frame Sync (Input) - Signals the start of a new TDM frame in the TDM digital interface format. Digital Power (Input) - Positive power supply for the digital section. Digital Ground (Input) - Ground reference for the digital section. Serial Port Interface Power (Input) - Determines the required signal level for the serial port interfaces. See "Digital I/O Pin Characteristics" on page 8. Serial Clock (Input) - Serial clock for the serial audio interface. Input frequency must be 256 x Fs. Master Clock (Input) - Clock source for the delta-sigma modulators and digital filters. Serial Audio Data Output (Output) - TDM output for two's complement serial audio data. DAC Serial Audio Data Input (Input) - TDM Input for two's complement serial audio data. Auxiliary Left/Right Clock (Output) - Determines which channel, Left or Right, is currently active on the Auxiliary serial audio data line. Auxiliary Serial Clock (Output) - Serial clock for the Auxiliary serial audio interface.
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CS42432
AUX_SDIN AOUT1 +,AOUT2 +,AOUT3 +,AOUT4 +,AOUT5 +,AOUT6 +,TSTO TSTN AGND VQ VA AIN1 +,AIN2 +,AIN3 +,AIN4 +,FILT+ 17 Auxiliary Serial Input (Input) - The 42432 provides an additional serial input for two's complement serial audio data.
20,19 21,22 Differential Analog Output (Output) - The full-scale differential analog output level is specified in 24,23 the Analog Characteristics specification table. Each positive leg of the differential outputs may 25,26 also be used single-ended. 28,27 29,30 31,32 Test Out - These pins are outputs used for test purposes only. They must not be connected to any 33,34 external trace or other connection. 49,50 Test In - These pins are inputs used for test purposes only. They must be tied to ground for nor51,52 mal operation. 35,48 Analog Ground (Input) - Ground reference for the analog section. 36 Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage.
37,46 Analog Power (Input) - Positive power supply for the analog section. 39,38 41,40 Differential Analog Input (Input) - Signals are presented differentially to the delta-sigma modula43,42 tors. The full-scale input level is specified in the Analog Characteristics specification table. 45,44 47 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
10
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CS42432 3. TYPICAL CONNECTION DIAGRAMS
+3.3 V 10 F + 0.01 F
0.01 F
+
+3.3 V to +5 V 10 F
0.01 F
8 37 46
VD
10
VA
VA AOUT1+ AOUT1AOUT2+ AOUT220 19 21 22 24 23 25 26 28 27 29 30
VLS
Analog Output Filter 2 Analog Output Filter 2 Analog Output Filter 2 Analog Output Filter 2 Analog Output Filter 2 Analog Output Filter 2
0.01 F
16
CS5341 A/D Converter
15 17
AUX_SCLK AUX_LRCK AUX_SDIN
AOUT3+ AOUT3AOUT4+ AOUT4AOUT5+ AOUT5AOUT6+ AOUT6-
12 11
MCLK SCLK FS DAC_SDIN AIN1+ AIN139 38 41 40
+1.8 V to +5.0 V
7
Digital Audio Processor
14
Input Filter 1 Input Filter 1
Analog Input 1
13
ADC_SDOUT
AIN2+ AIN2AIN3+
Analog Input 2
43 42 45 44
5
MicroController
RST SCL/CCLK SDA/CDOUT AD1/CDIN AD0/CS
AIN3AIN4+ AIN4-
Input Filter 1 Input Filter 1
Analog Input 3
1 2 4 3
Analog Input 4
** 2 k +1.8 V to +5 V
** Resistors are required for I2C control port operation
**
2 k
6
VLC VQ FILT+
37 47
0.1 F
+ DGND DGND
9 18
+ 100 F 0.1 F 4.7 F
AGND
35
AGND
48
0.1 F
Connect DGND and AGND at Codec
1. See the ADC Input Filter section in the Appendix. 2. See the DAC Output Filter section in the Appendix.
Figure 1. Typical Connection Diagram (Software Mode)
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CS42432
+3.3 V 10 F + 0.01 F
0.01 F
+
+3.3 V to +5 V 10 F
0.01 F
8 37 46
VD
10
VA
VA
VLS 0.01 F AOUT1+ AOUT1AOUT2+ AOUT216
20 19 21 22 24 23 25 26 28 27 29 30
Analog Output Filter 2 Analog Output Filter 2 Analog Output Filter 2 Analog Output Filter 2 Analog Output Filter 2 Analog Output Filter 2
CS5341 A/D Converter
15 17
AUX_SCLK AUX_LRCK AUX_SDIN
AOUT3+ AOUT3AOUT4+ AOUT4AOUT5+ AOUT5AOUT6+ AOUT6-
12 11
MCLK SCLK FS DAC_SDIN AIN1+ AIN139 38 41 40
+1.8 V to +5.0 V
7 14
Input Filter 1 Input Filter 1
Analog Input 1
Digital Audio Processor
13
ADC_SDOUT
AIN2+ AIN2AIN3+ AIN3-
Analog Input 2
43 42 45 44
Input Filter 1 Input Filter 1
Analog Input 3
5 3
RST AIN4+ MFREQ AIN4-
Analog Input 4
6
VLC
0.1 F
VQ FILT+
37 47
+ DGND DGND
9 18
+ 100 F 0.1 F 4.7 F
AGND
35
AGND
48
0.1 F
Connect DGND and AGND at Codec
1. See the ADC Input Filter section in the Appendix. 2. See the DAC Output Filter section in the Appendix.
Figure 2. Typical Connection Diagram (Hardware Mode)
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CS42432 4. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS
(AGND=DGND=0 V, all voltages with respect to ground.) Parameters DC Power Supply Analog Digital Serial Audio Interface Control Port Interface Ambient Temperature Commercial Automotive (Note 1) (Note 2) Symbol VA VD VLS VLC TA Min 3.14 3.14 1.71 1.71 -10 -40 Max 5.25 3.47 5.25 5.25 +70 +105 Units V V V V C C
-CMZ -DMZ
ABSOLUTE MAXIMUM RATINGS
(AGND = DGND = 0 V; all voltages with respect to ground.) Parameters DC Power Supply Analog Digital Serial Port Interface Control Port Interface (Note 3) (Note 4) Serial Port Interface Control Port Interface Symbol VA VD VLS VLC Iin VIN VIND-S VIND-C TA Tstg Min -0.3 -0.3 -0.3 -0.3 AGND-0.7 -0.3 -0.3 -50 -65 Max 6.0 6.0 6.0 6.0 10 VA+0.7 VLS+ 0.4 VLC+ 0.4 +125 +150 Units V V V V mA V V V C C
Input Current Analog Input Voltage Digital Input Voltage (Note 4) Ambient Operating Temperature (power applied) Storage Temperature
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 1. Typical Analog input/output performance will slightly degrade at VA = 3.3 V. 2. The ADC_SDOUT may not meet timing requirements in Double-Speed Mode. 3. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause SCR latch-up. 4. The maximum over/under voltage is limited by the input current.
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CS42432 ANALOG INPUT CHARACTERISTICS (COMMERCIAL)
(Test Conditions (unless otherwise specified): TA = -10 to +70C; VD = VLS = VLC = 3.3 V5%, VA = 5 V5%; Full-scale input sine wave: 1 kHz through the active input filter in Figure 19 on page 48 and Figure 20 on page 48; Measurement Bandwidth is 10 Hz to 20 kHz.)
Differential Parameter Fs=48 kHz, 96 kHz Dynamic Range Min Typ Max Min
Single-Ended Typ Max Unit
A-weighted 99 105 96 102 dB unweighted 96 102 93 99 dB 40 kHz bandwidth unweighted 99 96 dB dB -89 -95 -92 -98 Total Harmonic Distortion + Noise -1 dB dB -79 -82 (Note 5) -20 dB dB -39 -42 -60 dB dB -90 -90 40 kHz bandwidth -1 dB ADC1-2 Interchannel Isolation 90 90 dB DC Accuracy Interchannel Gain Mismatch 0.1 0.1 dB Gain Drift 100 100 ppm/C Analog Input Full-Scale Input Voltage 1.06*VA 1.12*VA 1.18*VA 0.53*VA 0.56*VA 0.59*VA Vpp Differential Input Impedance (Note 6) 18 k Single-Ended Input Impedance (Note 7) 18 k Common Mode Rejection Ratio (CMRR) 82 dB
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CS42432 ANALOG INPUT CHARACTERISTICS (AUTOMOTIVE)
(Test Conditions (unless otherwise specified): TA = -40 to +85C; VD = VLS = VLC = 3.3 V5%, VA = 5 V5%; Full-scale input sine wave: 1 kHz through the active input filter in Figure 19 on page 48 and Figure 20 on page 48; Measurement Bandwidth is 10 Hz to 20 kHz.)
Differential Parameter Fs=48 kHz, 96 kHz Dynamic Range Min Typ Max Min
Single-Ended Typ Max Unit
A-weighted 97 105 94 102 dB unweighted 94 102 91 99 dB 40 kHz bandwidth unweighted 99 96 dB dB -87 -95 -90 -98 Total Harmonic Distortion + Noise -1 dB dB -79 -82 (Note 5) -20 dB dB -39 -42 -60 dB dB -87 -87 40 kHz bandwidth -1 dB ADC1-2 Interchannel Isolation 90 90 dB DC Accuracy Interchannel Gain Mismatch 0.1 0.1 dB Gain Drift 100 100 ppm/C Analog Input Full-Scale Input Voltage 1.04*VA 1.12*VA 1.20*VA 0.52*VA 0.56*VA 0.60*VA Vpp Differential Input Impedance (Note 6) 18 k Single-Ended Input Impedance (Note 7) 18 k Common Mode Rejection Ratio (CMRR) 82 dB Notes: 5. Referred to the typical full-scale voltage. 6. Measured between AINx+ and AINx-. 7. Measured between AINxx and AGND.
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CS42432 ADC DIGITAL FILTER CHARACTERISTICS
Parameter (Notes 8, 9) Single-Speed Mode (Note 9) Passband (Frequency Response) Passband Ripple Stopband Stopband Attenuation Total Group Delay Double-Speed Mode (Note 9) Passband (Frequency Response) Passband Ripple Stopband Stopband Attenuation Total Group Delay High-Pass Filter Characteristics Frequency Response Phase Deviation Passband Ripple Filter Settling Time Notes: 8. Filter response is guaranteed by design. 9. Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 25 to 32) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. -3.0 dB -0.13 dB @ 20 Hz 1 20 10 10 /Fs
5
Min to -0.1 dB corner 0 0.5688 70 to -0.1 dB corner 0 0.5604 69 -
Typ 12/Fs 9/Fs
Max 0.4896 0.08 0.4896 0.16 0 0
Unit Fs dB Fs dB s Fs dB Fs dB s Hz Hz Deg dB s
16
DS673F1
CS42432 ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL)
(Test Conditions (unless otherwise specified): TA = -10 to +70C; VD = VLS = VLC = 3.3 V5%, VA = 5 V5%; Full-scale 997 Hz output sine wave (see Note 11) into passive filter in Figure 25 on page 51 and active filter in Figure 25 on page 51; Measurement Bandwidth is 10 Hz to 20 kHz.) Differential Typ Single-Ended Typ Max
Parameter Min Fs = 48 kHz, 96 kHz, 192 kHz Dynamic Range 102 18 to 24-Bit A-weighted 99 unweighted 16-Bit A-weighted unweighted Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB Interchannel Isolation (1 kHz) Analog Output Full-Scale Output 1.235*VA Interchannel Gain Mismatch Gain Drift Output Impedance DC Current draw from an AOUT pin (Note 10) AC-Load Resistance (RL) (Note 12) 3 Load Capacitance (CL) (Note 12) -
Max
Min
Unit
108 105 99 96 -98 -85 -45 -93 -76 -36 100
-92 -
99 96 -
105 102 96 93 -95 -82 -42 -90 -73 -33 100
-89 -
dB dB dB dB dB dB dB dB dB dB dB
1.300*VA 1.365*VA 0.618*VA 0.650*VA 0.683*VA Vpp 0.1 0.25 0.1 0.25 dB 100 100 ppm/C 100 100 10 10 A 100 3 100 k pF
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CS42432 ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE)
(Test Conditions (unless otherwise specified): TA = -40 to +85C; VD = VLS = VLC = 3.3 V5%, VA = 5 V5%; Full-scale 997 Hz output sine wave (see Note 11) in Figure 25 on page 51 and Figure 25 on page 51; Measurement Bandwidth is 10 Hz to 20 kHz.) Differential Typ Single-Ended Typ Max
Parameter Min Fs = 48 kHz, 96 kHz, 192 kHz Dynamic Range 100 18 to 24-Bit A-weighted 97 unweighted 16-Bit A-weighted unweighted Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB Interchannel Isolation (1 kHz) Analog Output Full-Scale Output 1.210*VA Interchannel Gain Mismatch Gain Drift Output Impedance DC Current draw from an AOUT pin (Note 10) AC-Load Resistance (RL) (Note 12) 3 Load Capacitance (CL) Notes: (Note 12) -
Max
Min
Unit
108 105 99 96 -98 -85 -45 -93 -76 -36 100
-90 -
97 94 -
105 102 96 93 -95 -82 -42 -90 -73 -33 100
-87 -
dB dB dB dB dB dB dB dB dB dB dB
1.300*VA 1.392*VA 0.605*VA 0.650*VA 0.696*VA Vpp 0.1 0.25 0.1 0.25 dB 100 100 ppm/C 100 100 10 10 A 100 3 100 k pF
10. Guaranteed by design. The DC current draw represents the allowed current draw from the AOUT pin due to typical leakage through the electrolytic DC-blocking capacitors. 11. One-half LSB of triangular PDF dither is added to data. 12. Guaranteed by design. See 3. RL and CL reflect the recommended minimum resistance and maximum capacitance required for the internal op-amp's stability and signal integrity. In this circuit topology, CL will effectively move the dominant pole of the two-pole amp in the output stage. Increasing this value beyond the recommended 100 pF can cause the internal op-amp to become unstable. See "External Filters" on page 48 for a recommended output filter.
18
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CS42432
125 Capacitive Load -- C L (pF) 100 75 50 25 Safe Operating Region
DAC1-3 AOUTxx
3.3 F +
Analog Output
RL CL
AGND
2.5 3
5 10 15 20
Resistive Load -- RL (k )
Figure 3. Output Test Load
Figure 4. Maximum Loading
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CS42432 COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
Parameter (Notes 8, 13) Single-Speed Mode Passband (Frequency Response) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay De-emphasis Error (Note 15) Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz (Note 14) to -0.05 dB corner to -3 dB corner 0 0 -0.2 0.5465 50 10/Fs 0.4780 0.4996 +0.08 Fs Fs dB Fs dB s Min Typ Max Unit
+1.5/+0 dB +0.05/-0.25 dB -0.2/-0.4 dB
Double-Speed Mode Passband (Frequency Response) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay Quad-Speed Mode Passband (Frequency Response) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay Notes: 13. Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 33 to 44) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 14. Single- and Double-Speed Mode Measurement Bandwidth is from Stopband to 3 Fs. Quad-Speed Mode Measurement Bandwidth is from Stopband to 1.34 Fs. 15. De-emphasis is only available in Single-Speed Mode. (Note 14) to -0.1 dB corner to -3 dB corner 0 0 -0.2 0.7 51 2.5/Fs 0.397 0.476 +0.05 Fs Fs dB Fs dB s (Note 14) to -0.1 dB corner to -3 dB corner 0 0 -0.2 0.5770 55 5/Fs 0.4650 0.4982 +0.7 Fs Fs dB Fs dB s
20
DS673F1
CS42432 SWITCHING SPECIFICATIONS - ADC/DAC PORT
(Inputs: Logic 0 = DGND, Logic 1 = VLS, ADC_SDOUT CLOAD = 15 pF.) Parameters Slave Mode RST pin Low Pulse Width MCLK Frequency MCLK Duty Cycle Input Sample Rate (FS pin) (Note 16) (Note 17) Single-Speed Mode Double-Speed Mode (Note 18) Quad-Speed Mode (Note 19) 1 0.512 45 4 50 100 45 8 8 5 16 3 5 5 10 15 50 55 50 100 200 55 ms MHz % kHz kHz kHz % ns ns ns ns ns ns ns ns ns Symbol Min Max Units
Fs Fs Fs tsckh tsckl tfss tfsh tds tdh tdh1 tdh2 tdval
SCLK Duty Cycle SCLK High Time SCLK Low Time FS Rising Edge to SCLK Rising Edge SCLK Rising Edge to FS Falling Edge DAC_SDIN Setup Time Before SCLK Rising Edge DAC_SDIN Hold Time After SCLK Rising Edge DAC_SDIN Hold Time After SCLK Rising Edge ADC_SDOUT Hold Time After SCLK Rising Edge ADC_SDOUT Valid Before SCLK Rising Edge
Notes: 16. After powering up the CS42432, RST should be held low after the power supplies and clocks are settled. 17. See Table 5 on page 41 for suggested MCLK frequencies. 18. VLS is limited to nominal 2.5 V to 5.0 V operation only. 19. ADC does not meet timing specification for Quad-Speed Mode.
FS
(input)
tfss
SCLK
(input)
tfsh
tsckh
tsckl
tds
DAC_SDIN
tdh1
MSB MSB-1
tdh2
ADC_SDOUT
MSB
tdval
MSB-1
Figure 5. TDM Serial Audio Interface Timing DS673F1 21
CS42432 SWITCHING CHARACTERISTICS - AUX PORT
(Inputs: Logic 0 = DGND, Logic 1 = VLS.) Parameters Master Mode Output Sample Rate (AUX_LRCK) AUX_SCLK Frequency AUX_SCLK Duty Cycle AUX_LRCK Edge to SCLK Rising Edge AUX_SDIN Setup Time Before SCLK Rising Edge AUX_SDIN Hold Time After SCLK Rising Edge tlcks tds tdh All Speed Modes Fs 45 3 5 LRCK 64*LRCK 55 5 kHz kHz % ns ns ns Symbol Min Max Units
AUX_LRCK
tlcks
tsckh
tsckl
AUX_SCLK
tds
AUX_SDIN
tdh
MSB MSB-1
Figure 6. Serial Audio Interface Slave Mode Timing
22
DS673F1
CS42432 SWITCHING SPECIFICATIONS - CONTROL PORT - IC MODE
(VLC = 1.8 V - 5.0 V, VLS = VD = 3.3 V, VA = 5.0 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, SDA CL = 30 pF) Parameter SCL Clock Frequency RST Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of SCL and SDA Fall Time SCL and SDA Setup Time for Stop Condition Acknowledge Delay from SCL Falling Notes: 20. Data must be held for sufficient time to bridge the transition time, tfc, of SCL. 21. Guaranteed by design. (Note 21) (Note 21) (Note 20) Symbol fscl tirs tbuf thdst tlow thigh tsust thdd tsud trc tfc tsusp tack Min 500 4.7 4.0 4.7 4.0 4.7 0 250 4.7 300 Max 100 1 300 1000 Unit kHz ns s s s s s s ns s ns s ns
RST t Stop irs Start R e p e a te d Sta rt t rd t fd Stop
SDA t buf t hdst t high t hdst t fc t susp
SCL t t t sud t ack t sust t rc
lo w
hdd
Figure 7. Control Port Timing - IC Format
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CS42432 SWITCHING SPECIFICATIONS - CONTROL PORT - SPI FORMAT
(VLC = 1.8 V - 5.0 V, VLS = VD = 3.3 V, VA = 5.0 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, CDOUT CL = 30 pF) Parameter CCLK Clock Frequency RST Rising Edge to CS Falling CS Falling to CCLK Edge CS High Time Between Transmissions CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time CCLK Falling to CDOUT Stable Rise Time of CDOUT Fall Time of CDOUT Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN Notes: 22. Data must be held for sufficient time to bridge the transition time of CCLK. 23. For fsck <1 MHz.
RST
Symbol fsck tsrs tcss tcsh tscl tsch tdsu (Note 22) tdh tpd tr1 tf1 (Note 23) (Note 23) tr2 tf2
Min 0 20 20 1.0 66 66 40 15 -
Max 6.0 50 25 25 100 100
Units MHz ns ns s ns ns ns ns ns ns ns ns ns
tsrs
CS
tcsh tcss tsch tscl tr2
CCLK
tf2 tdsu tdh
CDIN
tpd
MSB
CDOUT
MSB
Figure 8. Control Port Timing - SPI Format
24
DS673F1
CS42432 DC ELECTRICAL CHARACTERISTICS
(AGND = 0 V; all voltages with respect to ground.) Parameters Normal Operation (Note 24) Power Supply Current Symbol IA IDT PSRR Min Typ 80 60.6 600 60 40 1.25 0.5*VA 23 VA Max 850 10 Units mA mA mW dB dB mW V k A V
Power Dissipation Power Supply Rejection Ratio (Note 26) Power-Down Mode (Note 27) Power Dissipation VLS = VLC = VD = 3.3 V,VA = 5 V VQ Characteristics Nominal Voltage Output Impedance DC Current Source/Sink (Note 28) FILT+ Nominal Voltage Notes:
VA = 5.0 V VLS = VLC = VD = 3.3 V (Note 25) VLS = VLC = VD = 3.3 V,5 V 1 kHz 60 Hz
24. Normal operation is defined as RST = HI with a 997 Hz, 0 dBFS input to the DAC and AUX port, and a 1 kHz, -1 dB analog input to the ADC port sampled at the highest Fs for each speed mode. DAC outputs are open, unless otherwise specified. 25. IDT measured with no external loading on pin (SDA). 26. Valid with the recommended capacitor values on FILT+ and VQ. Increasing the capacitance will also increase the PSRR. 27. Power-Down Mode is defined as RST = LO with all clocks and data lines held static and no analog input. 28. Guaranteed by design. The DC current draw represents the allowed current draw from the VQ pin due to typical leakage through the electrolytic de-coupling capacitors.
DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS
Parameters (Note 29) High-Level Output Voltage at Io=2 mA Low-Level Output Voltage at Io=2 mA High-Level Input Voltage Low-Level Input Voltage Leakage Current Input Capacitance (Note 21) Notes: 29. See "Digital I/O Pin Characteristics" on page 8 for serial and control port power rails. Symbol Serial Port Control Port Serial Port Control Port Serial Port Control Port Serial Port Control Port VOH VOL VIH VIL Iin Min VLS-1.0 VLC-1.0 0.7xVLS 0.7xVLC Typ Max 0.4 0.4 0.2xVLS 0.2xVLC 10 10 Units V V V V V V V V A pF
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25
CS42432 5. APPLICATIONS
5.1 Overview
The CS42432 is a highly integrated mixed signal 24-bit audio CODEC comprised of 4 analog-to-digital converters (ADC) implemented using multi-bit delta-sigma techniques and 6 digital-to-analog converters (DAC) also implemented using multi-bit delta-sigma techniques. Other functions integrated within the CODEC include independent digital volume controls for each DAC, digital de-emphasis filters for the DAC, digital volume control with gain on each ADC channel, ADC high-pass filters, and an on-chip voltage reference,. The serial audio interface ports allow up to 6 DAC channels and 6 ADC channels in a Time-Division Multiplexed (TDM) interface format. The CS42432 features an Auxiliary Port used to accommodate an additional two channels of PCM data on the ADC_SDOUT data line in the TDM digital interface format. See "AUX Port Digital Interface Formats" on page 32 for details. The CS42432 operates in one of three oversampling modes based on the input sample rate. Mode selection is determined automatically based on the MCLK frequency setting. Single-Speed Mode (SSM) supports input sample rates up to 50 kHz and uses a 128x oversampling ratio. Double-Speed Mode (DSM) supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-Speed Mode (QSM) supports input sample rates up to 200 kHz and uses an oversampling ratio of 32x (Note: QSM for the ADC is only supported in the IS, Left-Justified, Right-Justified interface formats. QSM is not supported for the ADC). Note: QSM is only available in Software Mode (see "System Clocking" on page 31 for details). All functions can be configured through software via a serial control port operable in SPI Mode or in IC Mode. A Hardware, Stand-Alone Mode is also available, allowing configuration of the CODEC on a more limited basis. See Table 2 for the default configuration in Hardware Mode. Figure 1 on page 11 and Figure 2 on page 12 show the recommended connections for the CS42432 in Software and Hardware Mode, respectively. See "Register Description" on page 39 for the default register settings and options in Software Mode. Hardware Mode Feature Summary Function
Power Down ADC Power Down DAC Power Down Device MCLK Frequency Select Freeze Control AUX Serial Port Interface Format ADC1/ADC2 High Pass Filter Freeze DAC De-Emphasis ADC1/ADC2 Single-Ended Mode DAC Volume Control/Mute/Invert ADC Volume Control DAC Soft Ramp/Zero Cross ADC Soft Ramp/Zero Cross DAC Auto-Mute
Default Configuration
All ADC's are enabled All DAC's are enabled Device is powered up Selectable between 256Fs and 512Fs N/A Left-Justified High Pass Filter is always enabled No De-Emphasis applied Disabled All DAC Volume = 0 dB, unmuted, not inverted All ADC Volume = 0 dB Immediate Change Immediate Change Enabled
Hardware Control
"MFREQ" pin 3 -
Note
see Section 5.4 -
Table 2. Hardware Configurable Settings 26 DS673F1
CS42432
Hardware Mode Feature Summary Function
Status Interrupt
Default Configuration
N/A
Hardware Control
-
Note
Table 2. Hardware Configurable Settings (Continued)
5.2 5.2.1
Analog Inputs Line-Level Inputs
AINx+ and AINx- are the line-level differential analog inputs internally biased to VQ, approximately VA/2. Figure 9 on page 27 shows the full-scale analog input levels. The CS42432 also accommodates singleended signals on all inputs, AIN1-AIN4. See "ADC Input Filter" on page 48 for the recommended input filters.
5.2.1.1
Hardware Mode
AIN Volume Control and ADC Overflow status are not accessible in Hardware Mode.
5.2.1.2
Software Mode
For single-ended operation on ADC1-ADC2 (AIN1 to AIN4), the ADCx_SINGLE bit in the register "ADC Control & DAC De-Emphasis (Address 05h)" on page 42 must be set appropriately (see Figure 20 on page 48 for required external components). The gain/attenuation of the signal can be adjusted for each AINx independently through the "AINX Volume Control (Address 11h-14h)" on page 45. The ADC output data is in 2's complement binary format. For inputs above positive full scale or below negative full scale, the ADC will output 7FFFFFH or 800000H, respectively, and cause the ADC Overflow bit in the register "Status (Address 19h) (Read Only)" on page 46 to be set to a `1'.
5.0 V
3.9 V 2.5 V 1.1 V
VA AINx+
3.9 V 2.5 V 1.1 V
AINx-
Full-Scale Differential Input Level = (AINx+) - (AINx-) = 5.6 VPP = 1.98 VRMS
Figure 9. Full-Scale Input
5.2.2
High-Pass Filter and DC Offset Calibration
The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation filter. If the high-pass filter is disabled during normal operation, the current value of the DC offset for the corresponding channel is frozen and this DC offset will continue to be subtracted from the conversion result. This feature makes it possible to perform a system DC offset calibration by:
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27
CS42432
1. Running the CS42432 with the high-pass filter enabled until the filter settles. See the Digital Filter Characteristics for filter settling time. 2. Disabling the high-pass filter and freezing the stored DC offset.
5.2.2.1
Hardware Mode
The high pass filters for ADC1 and ADC2 are permanently enabled in Hardware Mode.
5.2.2.2
Software Mode
The high-pass filter for ADC1/ADC2 can be enabled and disabled. The high-pass filters are controlled using the HPF_FREEZE bit in the register "ADC Control & DAC De-Emphasis (Address 05h)" on page 42.
5.3 5.3.1
Analog Outputs Initialization
The initialization and Power-Down sequence flow chart is shown in Figure 10 on page 29. The CS42432 enters a power-down state upon initial power-up. The interpolation and decimation filters, delta-sigma modulators and control port registers are reset. The internal voltage reference, multi-bit digital-to-analog and analog-to-digital converters and switched-capacitor low-pass filters are powered down. The device remains in the power-down state until the RST pin is brought high. The control port is accessible once RST is high, and the desired register settings can be loaded per the interface descriptions in the "Control Port Description and Timing" on page 33. In Hardware Mode operation, the Hardware Mode pins must be set up before RST is brought high. All features will default to the Hardware Mode defaults as listed in Table 2. Once MCLK is valid, VQ will quickly charge to VA/2, and the internal voltage reference, FILT+, will begin powering up to normal operation. Power is applied to the D/A converters and switched-capacitor filters, and the analog outputs are clamped to the quiescent voltage, VQ. Once LRCK is valid, MCLK occurrences are counted over one LRCK period to determine the MCLK/LRCK frequency ratio. After an approximate 2000 sample period delay, normal operation begins.
5.3.2
Line-Level Outputs and Filtering
The CS42432 contains on-chip buffer amplifiers capable of producing line-level differential as well as single-ended outputs on AOUT1-AOUT6. These amplifiers are biased to a quiescent DC level of approximately VQ. The delta-sigma conversion process produces high-frequency noise beyond the audio passband, most of which is removed by the on-chip analog filters. The remaining out-of-band noise can be attenuated using an off-chip low-pass filter. See "DAC Output Filter" on page 50 for recommended output filter. The active filter configuration accounts for the normally differing AC loads on the AOUTx+ and AOUTx- differential output pins. Also shown is a passive filter configuration which minimizes costs and the number of components. Figure 11 shows the full-scale analog output levels. All outputs are internally biased to VQ, approximately VA/2.
28
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CS42432
No Power 1. VQ = ? 2. Aout bias = ? 3. No audio signal generated.
PDN bit = '1'b?
Yes
Power-Down 1. VQ discharge to 0 V. 2. Aout bias = Hi-Z. 3. No audio signal generated. 4. Control Port Registers retain settings.
No Power-Down (Power Applied) 1. VQ = 0 V. 2. Aout = HI-Z. 3. No audio signal generated. 4. Control Port Registers reset to default. Power-Up 1. VQ = VA/2. 2. Aout bias = VQ. RST = Low? Yes
No
Control Port Accessed
Sub-Clocks Applied 1. LRCK valid. 2. SCLK valid. 3. Audio samples processed.
No
Control Port Access Detected?
Yes
No Valid MCLK/LRCK Ratio? Yes
Hardware Mode H/W pins setup to desired settings.
Software Mode Registers setup to desired settings.
No No Valid MCLK Applied? Valid MCLK Applied? 2000 LRCK delay Yes Yes
RST = Low ERROR: Power removed
Normal Operation 1. VQ = VA/2. 2. Aout bias = VA/2. 3. Audio signal generated per register settings.
PDN bit set to '1'b
ERROR: MCLK/LRCK ratio change ERROR: MCLK removed
Analog Output Mute 1. VQ = VA/2. 2. Aout bias = VA/2. 3. No audio signal generated.
Analog Output Freeze 1. VQ = VA/2. 2. Aout bias = VA/2 + last audio sample. 3. No audio signal generated.
Figure 10. Audio Output Initialization Flow Chart
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29
CS42432
5.0 V
VA AOUTx+
2.5 V
4.125 V
0.875 V
4.125 V
AOUTx-
2.5 V 0.875 V
Full-Scale Differential Output Level = (AOUTx+) - (AOUTx-) = 6.5 VPP = 2.3 VRMS
Figure 11. Full-Scale Output
5.3.3
Digital Volume Control 5.3.3.1 Hardware Mode
DAC Volume Control and Mute are not accessible in Hardware Mode.
5.3.3.2
Software Mode
Each DAC's output level is controlled via the Volume Control registers operating over the range of 0 to -127.5 dB attenuation with 0.5 dB resolution. See "AOUTX Volume Control (Addresses 08h-0D)" on page 45. Volume control changes are programmable to ramp in increments of 0.125 dB at the rate controlled by the SZC[1:0] bits in the Digital Volume Control register. See "Transition Control (Address 06h)" on page 43. Each output can be independently muted via mute control bits in the register "DAC Channel Mute (Address 07h)" on page 44. When enabled, each AOUTx_MUTE bit attenuates the corresponding DAC to its maximum value (-127.5 dB). When the AOUTx_MUTE bit is disabled, the corresponding DAC returns to the attenuation level set in the Volume Control register. The attenuation is ramped up and down at the rate specified by the SZC[1:0] bits.
5.3.4
De-Emphasis Filter
The CS42432 includes on-chip digital de-emphasis optimized for a sample rate of 44.1 kHz. The filter response is shown in Figure 12. The de-emphasis feature is included to accommodate audio recordings that utilize 50/15 s pre-emphasis equalization as a means of noise reduction. De-emphasis is only available in Single-Speed Mode. Please see "DAC De-Emphasis Control (DAC_DEM)" on page 42 for de-emphasis control.
30
DS673F1
CS42432
Gain dB
T1=50 s 0dB
T2 = 15 s -10dB
F1 3.183 kHz
Frequency F2 10.61 kHz
Figure 12. De-Emphasis Curve
5.4
System Clocking
The CODEC serial audio interface ports operate as a slave andaccept externally generated clocks. The CODEC requires external generation of the master clock (MCLK). The frequency of this clock must be an integer multiple of, and synchronous with, the system sample rate, Fs.
5.4.1
Hardware Mode
The allowable ratios include 256Fs and 512Fs in Single-Speed Mode and 256Fs in Double-Speed Mode. The frequency of MCLK must be specified using the MFREQ (pin 3). See Table 3 for the required frequency range. Ratio (xFs) MFREQ Description SSM DSM QSM 0 1.5360 MHz to 12.8000 MHz 256 N/A N/A 1 2.0480 MHz to 25.6000 MHz 512 256 N/A Table 3. MCLK Frequency Settings
5.4.2
Software Mode
The frequency range of MCLK must be specified using the MFREQ bits in register "MCLK Frequency (MFREQ[2:0])" on page 41.
5.5
CODEC Digital Interface
The ADC and DAC serial ports operate as a slave and support the TDM digital interface formats with varying bit depths from 16 to 32 as shown in . Data is clocked out of the ADC on the falling edge of SCLK and clocked into the DAC on the rising edge. TDM is the only interface supported in Hardware and Software Mode.
5.5.1
TDM
TDM data is received most significant bit (MSB) first, on the second rising edge of the SCLK occurring after a an FS rising edge. All data is valid on the rising edge of SCLK. The AIN1 MSB is transmitted early, but is guaranteed valid for a specified time after SCLK rises. All other bits are transmitted on the falling edge of SCLK. Each time slot is 32 bits wide, with the valid data sample left `justified within the time slot. Valid data lengths are 16, 18, 20, or 24. SCLK must operate at 256Fs. FS identifies the start of a new frame and is equal to the sample rate, Fs.
DS673F1
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CS42432
FS is sampled as valid on the rising SCLK edge preceding the most significant bit of the first data sample
and must be held valid for at least 1 SCLK period. Note:
FS SCLK LSB MSB LSB MSB LSB MSB AOUT2 LSB MSB AOUT3 LSB MSB AOUT4 LSB MSB LSB MSB LSB MSB LSB MSB
The ADC does not meet the timing requirements for proper operation in Quad-Speed Mode.
Bit or Word Wide 256 clks
DAC_SDIN
AOUT1 32 clks ADC_SDOUT MSB AIN1 32 clks
AOUT5
AOUT6
32 clks 32 clks 32 clks 32 clks 32 clks 32 clks 32 clks LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB AIN2 32 clks AIN3 32 clks AIN4 32 clks 32 clks 32 clks AUX1 32 clks AUX2 32 clks
Figure 13. TDM Serial Audio Format
5.5.2
I/O Channel Allocation
Interface Digital Input/Output Format DAC_SDIN TDM ADC_SDOUT TDM Analog Output/Input Channel Allocation from/to Digital I/O AOUT 1,2,3,4,5,6 AIN 1,2,3,4 (2 additional channels from AUX_SDIN)
Table 4. Serial Audio Interface Channel Allocations
5.6
AUX Port Digital Interface Formats
These serial data lines are used when supporting the TDM Mode of operation with an external ADC or S/PDIF receiver attached. The AUX serial port operates only as a clock master. The AUX_SCLK will operate at 64xFs, where Fs is equal to the ADC sample rate (FS on the TDM interface). If the AUX_SDIN signal is not being used, it should be tied to AGND via a pull-down resistor.
5.6.1
Hardware Mode
The AUX port will only operate in the Left-Justified digital interface format and supports bit depths ranging from 16 to 24 bits (see Figure 17 on page 34 for timing relationship between AUX_LRCK and AUX_SCLK).
5.6.2
Software Mode
The AUX port will operate in either the Left-Justified or IS digital interface format with bit depths ranging from 16 to 24 bits. Settings for the AUX port are made through the register "Miscellaneous Control (Address 04h)" on page 41.
5.6.3
IS
L eft C h a n n el R ig ht C h a n n el
AUX_LRCK AUX_SCLK AUX_SDIN
MSB
LS B AUX1
M SB AUX2
LS B
MSB
Figure 14. AUX IS Format
32
DS673F1
CS42432
5.6.4 Left-Justified
L e ft C h a n n el R ig ht C h a n n el
AUX_LRCK AUX_SCLK AUX_SDIN
MSB
LS B AUX1
M SB AUX2
LS B
MSB
Figure 15. AUX Left-Justified Format
5.7
Control Port Description and Timing
The control port is used to access the registers, in Software Mode, allowing the CS42432 to be configured for the desired operational modes and formats. The operation of the control port may be completely asynchronous with respect to the audio sample rates. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. The control port has two modes: SPI and IC, with the CS42432 acting as a slave device. SPI Mode is selected if there is a high-to-low transition on the AD0/CS pin, after the RST pin has been brought high. IC Mode is selected by connecting the AD0/CS pin through a resistor to VLC or DGND, thereby permanently selecting the desired AD0 bit address state.
5.7.1
SPI Mode
In SPI Mode, CS is the CS42432 chip-select signal, CCLK is the control port bit clock (input into the CS42432 from the microcontroller), CDIN is the input data line from the microcontroller, CDOUT is the output data line to the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling edge. Figure 16 shows the operation of the control port in SPI Mode. To write to a register, bring CS low. The first seven bits on CDIN form the chip address and must be 1001111. The eighth bit is a read/write indicator (R/W), which should be low to write. The next eight bits form the Memory Address Pointer (MAP), which is set to the address of the register that is to be updated. The next eight bits are the data which will be placed into the register designated by the MAP. During writes, the CDOUT output stays in the Hi-Z state. It may be externally pulled high or low with a 47 k resistor, if desired. There is a MAP auto-increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero, the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will auto-increment after each byte is read or written, allowing block reads or writes of successive registers. To read a register, the MAP has to be set to the correct address by executing a partial write cycle which finishes (CS high) immediately after the MAP byte. The MAP auto-increment bit (INCR) may be set or not, as desired. To begin a read, bring CS low, send out the chip address and set the read/write bit (R/W) high. The next falling edge of CCLK will clock out the MSB of the addressed register (CDOUT will leave the high impedance state). If the MAP auto-increment bit is set to 1, the data for successive registers will appear consecutively.
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CS42432
CS
CC LK C H IP ADDRESS C D IN 1001111 R/W C H IP ADDRESS LSB b y te n MSB LSB MSB LSB
MAP MSB
DATA
1001111
R/W
b y te 1 High Impedance CDOUT
MAP = Memory Address Pointer, 8 bits, MSB first
Figure 16. Control Port Timing in SPI Mode
5.7.2
IC Mode
In IC Mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. There is no CS pin. Pins AD0 and AD1 form the two least-significant bits of the chip address and should be connected through a resistor to VLC or DGND as desired. The state of the pins is sensed while the CS42432 is being reset. The signal timings for a read and write cycle are shown in Figure 17 and Figure 18. A Start condition is defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS42432 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low for a write). The upper 5 bits of the 7-bit address field are fixed at 10010. To communicate with a CS42432, the chip address field, which is the first byte sent to the CS42432, should match 10010 followed by the settings of the AD1 and AD0. The eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the Memory Address Pointer (MAP) which selects the register to be read or written. If the operation is a read, the contents of the register pointed to by the MAP will be output. Setting the auto-increment bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. The ACK bit is output from the CS42432 after each input byte is read, and is input to the CS42432 from the microcontroller after each transmitted byte.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 24 25 26 27 28
SCL
CHIP ADDRESS (WRITE) MAP BYTE
INCR
DATA
2 1 0 7 6 1 0 7
DATA +1
6 1 0 7
DATA +n
6 1 0
SDA
START
1
0
0
1
0 AD1 AD0 0
6
5
4
3
ACK
ACK
ACK
ACK STOP
Figure 17. Control Port Timing, IC Write
34
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CS42432
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
SCL
CHIP ADDRESS (WRITE) MAP BYTE
INCR
STOP
1 0 1
CHIP ADDRESS (READ)
0 0 1 0 AD1 AD0 1
DATA
7 0
DATA +1
7 0
DATA + n
7 0
SDA
1
0
0
1
0 AD1 AD0 0
6
5
4
3
2
ACK START
ACK START
ACK
ACK
NO ACK
STOP
Figure 18. Control Port Timing, IC Read Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown in Figure 18, the write operation is aborted after the acknowledge for the MAP byte by sending a stop condition. The following pseudocode illustrates an aborted write operation followed by a read operation. Send start condition. Send 10010xx0 (chip address & write operation). Receive acknowledge bit. Send MAP byte, auto increment off. Receive acknowledge bit. Send stop condition, aborting write. Send start condition. Send 10010xx1(chip address & read operation). Receive acknowledge bit. Receive byte, contents of selected register. Send acknowledge bit. Send stop condition. Setting the auto-increment bit in the MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit.
5.8 5.8.1
Recommended Power-Up Sequence Hardware Mode
1. Hold RST low until the power supply, clocks and hardware control pins are stable. In this state, the control port is reset to its default settings and VQ will remain low. 2. Bring RST high. The device will initially be in a low power state with VQ low. 3. The device will initiate the Hardware Mode power up sequence. All features will default to the Hardware Mode defaults as listed in Table 2 on page 26 according to the Hardware Mode control pins. VQ will quick-charge to approximately VA/2 and the analog output bias will clamp to VQ. 4. Following approximately 2000 sample periods, the device is initialized and ready for normal operation. Note: During the Hardware Mode power-up sequence, there must be no transitions on any of the hardware control pins.
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CS42432
5.8.2 Software Mode
1. Hold RST low until the power supply and clocks are stable. In this state, the control port is reset to its default settings and VQ will remain low. 2. Bring RST high. The device will initially be in a low power state with VQ low. All features will default as described in the "Register Quick Reference" on page 37. 3. Perform a write operation to the Power Control register ("Power Control (Address 02h)" on page 40) to set bit 0 to a `1'b. This will place the device in a power down state. 4. Load the desired register settings while keeping the PDN bit set to `1'b. 5. Mute all DACs. Muting the DACs suppresses any noise associated with the CODEC's first initialization after power is applied. 6. Set the PDN bit in the power control register to `0'b.Following approximately 2000 LRCK cycles, the device is initialized and ready for normal operation. 7. After the CODEC is initialized, wait ~90 LRCK cycles (~1.9 ms @48 kHz) and then unmute the DACs. 8. Normal operation begins.
5.9
Reset and Power-Up
It is recommended that reset be activated if the analog or digital supplies drop below the recommended operating condition to prevent power-glitch-related issues. The delta-sigma modulators settle in a matter of microseconds after the analog section is powered, either through the application of power or by setting the RST pin high. However, the voltage reference will take much longer to reach a final value due to the presence of external capacitance on the FILT+ pin. A time delay of approximately 400 ms is required after applying power to the device or after exiting a reset state. During this voltage reference ramp delay, all serial ports and DAC outputs will be automatically muted.
5.10
Power Supply, Grounding, and PCB Layout
As with any high-resolution converter, the CS42432 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. 1 and 2 show the recommended power arrangements, with VA connected to clean supplies. VD, which powers the digital circuitry, may be run from the system logic supply. Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling capacitors are recommended. Decoupling capacitors should be as near to the pins of the CS42432 as possible. The low value ceramic capacitor should be the nearest to the pin and should be mounted on the same side of the board as the CS42432 to minimize inductance effects. All signals, especially clocks, should be kept away from the FILT+, VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 F, must be positioned to minimize the electrical path from FILT+ and AGND. The CDB42438 evaluation board demonstrates the optimum layout and power supply arrangements. For optimal heat dissipation from the package, it is recommended that the area directly under the part be filled with copper and tied to the ground plane. The use of vias connecting the topside ground to the backside ground is also recommended.
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CS42432 6. REGISTER QUICK REFERENCE
Software Mode register defaults are as shown. Note: The default value in all "Reserved" registers must be preserved. Addr Function
01h 02h ID p 39 default Power Control p 40 default 03h Functional Mode p 41 default 04h Misc Control p 41 default 05h ADC Control
(w/DAC_DEM)
7
Chip_ID3 0 Reserved 0 Reserved 1 FREEZE 0 ADC1-2_HPF FREEZE 0 DAC_SNG VOL 0 Reserved 0 AOUT1 VOL7 0 AOUT2 VOL7 0 AOUT3 VOL7 0 AOUT4 VOL7 0 AOUT5 VOL7 0 AOUT6 VOL7 0 Reserved 0 Reserved 0 Reserved 0
6
Chip_ID2 0 PDN_ADC2 0 Reserved 1 AUX_DIF 0 Reserved 0 DAC_SZC1 0 Reserved 0 AOUT1 VOL6 0 AOUT2 VOL6 0 AOUT3 VOL6 0 AOUT4 VOL6 0 AOUT5 VOL6 0 AOUT6 VOL6 0 Reserved 0 Reserved 0 Reserved 0
5
Chip_ID1 0 PDN_ADC1 0 Reserved 1 Reserved 1 DAC_DEM 0 DAC_SZC0 0 AOUT6 MUTE 0 AOUT1 VOL5 0 AOUT2 VOL5 0 AOUT3 VOL5 0 AOUT4 VOL5 0 AOUT5 VOL5 0 AOUT6 VOL5 0 Reserved 0 Reserved 0
4
Chip_ID0 0 Reserved 0 Reserved 1 Reserved 1 ADC1 SINGLE 0 AMUTE 1 AOUT5 MUTE 0 AOUT1 VOL4 0 AOUT2 VOL4 0 AOUT3 VOL4 0 AOUT4 VOL4 0 AOUT5 VOL4 0 AOUT6 VOL4 0 Reserved 0 Reserved 0
3
Rev_ID3 0 PDN_DAC3 0 MFreq2 0 Reserved 0 ADC2 SINGLE 0 MUTE ADC_SP 0 AOUT4 MUTE 0 AOUT1 VOL3 0 AOUT2 VOL3 0 AOUT3 VOL3 0 AOUT4 VOL3 0 AOUT5 VOL3 0 AOUT6 VOL3 0 Reserved 0 Reserved 0
2
Rev_ID2 0 PDN_DAC2 0 MFreq1 0 Reserved
1
Rev_ID1 0 PDN_DAC1 0 MFreq0 0 Reserved 1 Reserved 0 ADC_SZC1 0 AOUT2 MUTE 0 AOUT1 VOL1 0 AOUT2 VOL1 0 AOUT3 VOL1 0 AOUT4 VOL1 0 AOUT5 VOL1 0 AOUT6 VOL1 0 Reserved 0 Reserved 0
0
Rev_ID0 1 PDN 0 Reserved 0 Reserved 0 Reserved 0 ADC_SZC0 0 AOUT1 MUTE 0 AOUT1 VOL0 0 AOUT2 VOL0 0 AOUT3 VOL0 0 AOUT4 VOL0 0 AOUT5 VOL0 0 AOUT6 VOL0 0 Reserved 0 Reserved 0
1
Reserved 0 ADC_SNG VOL 0 AOUT3 MUTE 0 AOUT1 VOL2 0 AOUT2 VOL2 0 AOUT3 VOL2 0 AOUT4 VOL2 0 AOUT5 VOL2 0 AOUT6 VOL2 0 Reserved 0 Reserved 0
p 42 default 06h Transition Control p 43 default 07h Channel Mute p 44 default 08h Vol. Control AOUT1 p 45 default 09h Vol. Control AOUT2 p 45 default 0Ah Vol. Control AOUT3 p 45 default 0Bh Vol. Control AOUT4 p 45 default 0Ch Vol. Control AOUT5 p 45 default 0Dh Vol. Control AOUT6 p 45 default 0Eh 0Fh 10h Reserved default Reserved default DAC Channel Invert p 45 default
INV_AOUT6 INV_AOUT5 INV_AOUT4 INV_AOUT3 INV_AOUT2 INV_AOUT1 0 0 0 0 0 0
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CS42432
Addr Function
11h Vol. Control AIN1 p 45 default 12h Vol. Control AIN2 p 45 default 13h Vol. Control AIN3 p 45 default 14h Vol. Control AIN4 p 45 default 15h 16h 17h Reserved default Reserved default ADC Channel Invert p 45 default 18h 19h Reserved default Status p 46 default 1Ah Status Mask p 47 default
7
AIN1 VOL7 0 AIN2 VOL7 0 AIN3 VOL7 0 AIN4 VOL7 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0
6
AIN1 VOL6 0 AIN2 VOL6 0 AIN3 VOL6 0 AIN4 VOL6 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0
5
AIN1 VOL5 0 AIN2 VOL5 0 AIN3 VOL5 0 AIN4 VOL5 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0
4
AIN1 VOL4 0 AIN2 VOL4 0 AIN3 VOL4 0 AIN4 VOL4 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0
3
AIN1 VOL3 0 AIN2 VOL3 0 AIN3 VOL3 0 AIN4 VOL3 0 Reserved 0 Reserved 0 INV_A4 0 Reserved 0 CLK Error
2
AIN1 VOL2 0 AIN2 VOL2 0 AIN3 VOL2 0 AIN4 VOL2 0 Reserved 0 Reserved 0 INV_A3 0 Reserved 0 Reserved X Reserved 0
1
AIN1 VOL1 0 AIN2 VOL1 0 AIN3 VOL1 0 AIN4 VOL1 0 Reserved 0 Reserved 0 INV_A2 0 Reserved 0 ADC2 OVFL X ADC2 OVFL_M 0
0
AIN1 VOL0 0 AIN2 VOL0 0 AIN3 VOL0 0 AIN4 VOL0 0 Reserved 0 Reserved 0 INV_A1 0 Reserved 0 ADC1 OVFL X ADC1 OVFL_M 0
X
X CLK Error_M
0
0
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CS42432 7. REGISTER DESCRIPTION
All registers are read/write except for the I.D. and Revision Register and Interrupt Status Register which are read only. See the following bit-definition tables for bit assignment information. The default state of each bit after a powerup sequence or reset is listed in each bit description.
7.1
7
Memory Address Pointer (MAP)
Not a register
6
MAP6
5
MAP5
4
MAP4
3
MAP3
2
MAP2
1
MAP1
0
MAP0
INCR
7.1.1
Increment (INCR)
Default = 1 Function: Memory address pointer auto increment control 0 - MAP is not incremented automatically. 1 - Internal MAP is automatically incremented after each read or write.
7.1.2
Memory Address Pointer (MAP[6:0])
Default = 0000001 Function: Memory address pointer (MAP). Sets the register address that will be read or written by the control port.
7.2
7
Chip I.D. and Revision Register (Address 01h) (Read Only)
6
Chip_ID2
5
Chip_ID1
4
Chip_ID0
3
Rev_ID3
2
Rev_ID2
1
Rev_ID1
0
Rev_ID0
Chip_ID3
7.2.1
Chip I.D. (CHIP_ID[3:0])
Default = 0000 Function: I.D. code for the CS42432. Permanently set to 0000.
7.2.2
Chip Revision (REV_ID[3:0])
Default = 0001 Function: CS42432 revision level. Revision A is coded as 0001.
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CS42432
7.3
7
Reserved
Power Control (Address 02h)
6
PDN_ADC2
5
PDN_ADC1
4
3
PDN_DAC3
2
PDN_DAC2
1
PDN_DAC1
0
PDN
Reserved
7.3.1
Power Down ADC Pairs (PDN_ADCX)
Default = 0 0 - Disable 1 - Enable Function: When enabled, the respective ADC channel pair (ADC1 - AIN1/AIN2; and ADC2 - AIN3/AIN4) will remain in a reset state.
7.3.2
Power Down DAC Pairs (PDN_DACX)
Default = 0 0 - Disable 1 - Enable Function: When enabled, the respective DAC channel pair (DAC1 - AOUT1/AOUT2; DAC2 - AOUT3/AOUT4; and DAC3 - AOUT5/AOUT6) will remain in a reset state. It is advised that any change of these bits be made while the DACs are muted or the power down bit (PDN) is enabled to eliminate the possibility of audible artifacts.
7.3.3
Power Down (PDN)
Default = 0 0 - Disable 1 - Enable Function: The entire device will enter a low-power state when this function is enabled. The contents of the control registers are retained in this mode.
40
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7.4
7
Functional Mode (Address 03h)
6 5 4 3
MFreq2
2
MFreq1
1
MFreq0
0
Reserved
Reserved
Reserved
Reserved
Reserved
7.4.1
MCLK Frequency (MFREQ[2:0])
Default = 000 Function: Sets the appropriate frequency for the supplied MCLK. For TDM operation, SCLK must equal 256Fs. MCLK can be equal to or greater than SCLK. Ratio (xFs) DSM N/A N/A 256 384 512
MFreq2
0 0 0 0 1
MFreq1
0 0 1 1 X
MFreq0
0 1 0 1 X
Description 1.0290 MHz to 12.8000 MHz 1.5360 MHz to 19.2000 MHz 2.0480 MHz to 25.6000 MHz 3.0720 MHz to 38.4000 MHz 4.0960 MHz to 51.2000 MHz
SSM 256 384 512 768 1024
QSM N/A N/A N/A N/A 256
Table 5. MCLK Frequency Settings
7.5
7
MISCELLANEOUS CONTROL (Address 04h)
6
AUX_DIF
5
4
3
2
1
0
FREEZE
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
7.5.1
Freeze Controls (FREEZE)
Default = 0 Function: This function will freeze the previous settings of, and allow modifications to be made to the channel mutes, the DAC and ADC Volume Control/Channel Invert registers without the changes taking effect until the FREEZE is disabled. To have multiple changes in these control port registers take effect simultaneously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit.
7.5.2
Auxiliary Digital Interface Format (AUX_DIF)
Default = 0 0 - Left Justified 1 - IS Function: This bit selects the digital interface format used for the AUX Serial Port. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in Figures 16-17.
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CS42432
7.6
7
ADC1-2_HPF FREEZE
ADC Control & DAC De-Emphasis (Address 05h)
6
Reserved
5
DAC_DEM
4
ADC1 SINGLE
3
ADC2 SINGLE
2
Reserved
1
Reserved
0
Reserved
7.6.1
ADC1-2 High-Pass Filter Freeze (ADC1-2_HPF FREEZE)
Default = 0 Function: When this bit is set, the internal high-pass filter will be disabled for ADC1 and ADC2.The current DC offset value will be frozen and continue to be subtracted from the conversion result. See "ADC Digital Filter Characteristics" on page 16.
7.6.2
DAC De-Emphasis Control (DAC_DEM)
Default = 0 0 - No De-Emphasis 1 - De-Emphasis Enabled (Auto-Detect Fs) Function: Enables the digital filter to maintain the standard 15s/50s digital de-emphasis filter response at the auto-detected sample rate of either 32, 44.1, or 48 kHz. De-emphasis will not be enabled, regardless of this register setting, at any other sample rate.
7.6.3
ADC1 Single-Ended Mode (ADC1 SINGLE)
Default = 0 0 - Disabled; Differential input to ADC1 1 - Enabled; Single-Ended input to ADC1 Function: When enabled, this bit allows the user to apply a single-ended input to the positive terminal of ADC1. A +6 dB digital gain is automatically applied to the serial audio data of ADC1. The negative leg must be driven to the common mode of the ADC. See Figure 20 on page 48 for a graphical description.
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CS42432
7.6.4 ADC2 Single-Ended Mode (ADC2 SINGLE)
Default = 0 0 - Disabled; Differential input to ADC2 1 - Enabled; Single-Ended input to ADC2 Function: When enabled, this bit allows the user to apply a single-ended input to the positive terminal of ADC2. A +6 dB digital gain is automatically applied to the serial audio data of ADC2. The negative leg must be driven to the common mode of the ADC. See Figure 20 on page 48 for a graphical description.
7.7
7
Transition Control (Address 06h)
6
DAC_SZC1
5
DAC_SZC0
4
AMUTE
3
MUTE ADC_SP
2
ADC_SNGVOL
1
ADC_SZC1
0
ADC_SZC0
DAC_SNGVOL
7.7.1
Single Volume Control (DAC_SNGVOL, ADC_SNGVOL)
Default = 0 Function: The individual channel volume levels are independently controlled by their respective Volume Control registers when this function is disabled. When enabled, the volume on all channels is determined by the AOUT1 and AIN1 Volume Control register and the other Volume Control registers are ignored.
7.7.2
Soft Ramp and Zero Cross Control (ADC_SZC[1:0], DAC_SZC[1:0])
Default = 00 00 - Immediate Change 01 - Zero Cross 10 - Soft Ramp 11 - Soft Ramp on Zero Crossings Function: Immediate Change When Immediate Change is selected, all volume-level changes will take effect immediately in one step. Zero Cross Zero Cross Enable dictates that signal level changes, either by gain changes, attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Soft Ramp Soft Ramp allows level changes, either by gain changes, attenuation changes or muting, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods. Soft Ramp on Zero Crossing
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CS42432
Soft Ramp and Zero Cross Enable dictates that signal level changes, either by gain changes, attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel.
7.7.3
Auto-Mute (AMUTE)
Default = 1 0 - Disabled 1 - Enabled Function: The Digital-to-Analog converters of the CS42432 will mute the output following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained during the mute period. The muting function is affected, similar to volume control changes, by the Soft and Zero Cross bits (SZC[1:0]).
7.7.4
Mute ADC Serial Port (MUTE ADC_SP)
Default = 0 0 - Disabled 1 - Enabled Function: When enabled, the ADC Serial Port will be muted.
7.8
7
DAC Channel Mute (Address 07h)
6 5
AOUT6_MUTE
4
AOUT5_MUTE
3
AOUT4_MUTE
2
AOUT3_MUTE
1
AOUT2_MUTE
0
AOUT1_MUTE
Reserved
Reserved
7.8.1
Independent Channel Mute (AOUTX_MUTE)
Default = 0 0 - Disabled 1 - Enabled Function: The respective Digital-to-Analog converter outputs of the CS42432 will mute when enabled. The quiescent voltage on the outputs will be retained. The muting function is affected by the DAC Soft and Zero Cross bits (DAC_SZC[1:0]).
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CS42432
7.9
7
AOUTx_VOL7
AOUTX Volume Control (Addresses 08h-0D)
6
AOUTx_VOL6
5
AOUTx_VOL5
4
AOUTx_VOL4
3
AOUTx_VOL3
2
AOUTx_VOL2
1
AOUTx_VOL1
0
AOUTx_VOL0
7.9.1
Volume Control (AOUTX_VOL[7:0])
Default = 00h Function: The AOUTx Volume Control registers allow independent setting of the signal levels in 0.5 dB increments from 0 dB to -127.5 dB. Volume settings are decoded as shown in Table 6. The volume changes are implemented as dictated by the Soft and Zero Cross bits (DAC_SZC[1:0]). All volume settings less than 127.5 dB are equivalent to enabling the AOUTx_MUTE bit for the given channel. Binary Code 00000000 00101000 01010000 01111000 10110100 Volume Setting 0 dB -20 dB -40 dB -60 dB -90 dB
Table 6. Example AOUT Volume Settings
7.10
7
DAC Channel Invert (Address 10h)
6 5
INV_AOUT6
4
INV_AOUT5
3
INV_AOUT4
2
INV_AOUT3
1
INV_AOUT2
0
INV_AOUT1
Reserved
Reserved
7.10.1 Invert Signal Polarity (INV_AOUTX)
Default = 0 0 - Disabled 1 - Enabled Function: When enabled, these bits will invert the signal polarity of their respective channels.
7.11
7
AINX Volume Control (Address 11h-14h)
6
AINx_VOL6
5
AINx_VOL5
4
AINx_VOL4
3
AINx_VOL3
2
AINx_VOL2
1
AINx_VOL1
0
AINx_VOL0
AINx_VOL7
7.11.1
AINX Volume Control (AINX_VOL[7:0])
Default = 00h Function: The level of AIN1 - AIN6 can be adjusted in 0.5 dB increments as dictated by the ADC Soft and Zero Cross bits (ADC_SZC[1:0]) from +24 to -64 dB. Levels are decoded in two's complement, as shown in Table 7.
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CS42432
Binary Code 0111 1111 *** 0011 0000 *** 0000 0000 1111 1111 1111 1110 *** 1000 0000 Volume Setting +24 dB *** +24 dB *** 0 dB -0.5 dB -1 dB *** -64 dB
Table 7. Example AIN Volume Settings
7.12
7
ADC Channel Invert (Address 17h)
6
Reserved
5
Reserved
4
Reserved
3
INV_AIN4
2
INV_AIN3
1
INV_AIN2
0
INV_AIN1
Reserved
7.12.1 Invert Signal Polarity (INV_AINX)
Default = 0 0 - Disabled 1 - Enabled Function: When enabled, these bits will invert the signal polarity of their respective channels.
7.13
7
Status (Address 19h) (Read Only)
6
Reserved
5
Reserved
4
Reserved
3
CLK Error
2
Reserved
1
ADC2_OVFL
0
ADC1_OVFL
Reserved
For all bits in this register, a "1" means the associated error condition has occurred at least once since the register was last read. A"0" means the associated error condition has NOT occurred since the last reading of the register. Reading the register resets all bits to 0. Status bits that are masked off in the associated mask register will always be "0" in this register.
7.13.1 CLOCK ERROR (CLK ERROR)
Default = x Function: Indicates an invalid MCLK to FS ratio. This status flag is set to "Level Active Mode" and becomes active during the error condition. See "System Clocking" on page 31 for valid clock ratios.
7.13.2 ADC Overflow (ADCX_OVFL)
Default = x Function: Indicates that there is an over-range condition anywhere in the CS42432 ADC signal path of each of the associated ADC's.
46
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CS42432
7.14
7
Reserved
Status Mask (Address 1Ah)
6
Reserved
5
Reserved
4
Reserved
3
CLK Error_M
2
Reserved
1
ADC2_OVFL_M
0
ADC1_OVFL_M
Default = 0000 Function: The bits of this register serve as a mask for the error sources found in the register "Status (Address 19h) (Read Only)" on page 46. If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will affect the status register. If a mask bit is set to 0, the error is masked, meaning that its occurrence will not affect status register. The bit positions align with the corresponding bits in the Status register.
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CS42432 8. EXTERNAL FILTERS
8.1 ADC Input Filter
The analog modulator samples the input at 6.144 MHz (internal MCLK=12.288 MHz). The digital filter will reject signals within the stopband of the filter. However, there is no rejection for input signals which are multiples of the digital passband frequency (n x 6.144 MHz), where n=0,1,2,... Refer to Figures 19 and 20 for a recommended analog input filter that will attenuate any noise energy at 6.144 MHz, in addition to providing the optimum source impedance for the modulators. Refer to Figures 21 and 22 for low-cost, low-componentcount passive input filters. The use of capacitors that have a large voltage coefficient (such as general-purpose ceramics) must be avoided since these can degrade signal linearity
634 470 pF C0G 4.7 F + 634 100 k 91 634 470 pF C0G + 100 k 0.1 F 100 F 332 91 2700 pF C0G
ADC1-2 AINx+
VA
100 k
10 k
AINx-
Figure 19. Single-to-Differential Active Input Filter
634 VA 100 k 4.7 F 100 k 100 k 470 pF + 2700 pF C0G C0G
ADC1-2
91
AIN1+,2+,3+,4+
4.7 F
AIN1-,2-,3-,4-
Figure 20. Single-Ended Active Input Filter
48
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CS42432
8.1.1 Passive Input Filter
The passive filter implementation shown in Figure 21 will attenuate any noise energy at 6.144 MHz but will not provide optimum source impedance for the ADC modulators. Full analog performance will therefore not be realized using a passive filter. Figure 21 illustrates the unity gain, passive input filter solution. In this topology the distortion performance is affected, but the dynamic range performance is not limited.
ADC1-2
150 100 k 10 F 2700 pF
C0G
AIN1+,2+,3+,4+
AIN1-,2-,3-,44.7 F
Figure 21. Passive Input Filter
8.1.2
Passive Input Filter w/Attenuation
Some applications may require signal attenuation prior to the ADC. The full-scale input voltage will scale with the analog power supply voltage. For VA = 5.0 V, the full-scale input voltage is approximately 2.8 Vpp, or 1 Vrms (most consumer audio line-level outputs range from 1.5 to 2 Vrms). Figure 22 shows a passive input filter with 6 dB of signal attenuation. Due to the relatively high input impedance on the analog inputs, the full distortion performance cannot be realized. Also, the resistor divider circuit will determine the input impedance into the input filter. In the circuit shown in Figure 22, the input impedance is approximately 5 k. By doubling the resistor values, the input impedance will increase to 10 k. However, in this case the distortion performance will drop due to the increase in series resistance on the analog inputs.
ADC1-2 AIN1+,2+,3+,4+
2.5 k 2700 pF
C0G
2.5 k
10 F
AIN1-,2-,3-,44.7 F
Figure 22. Passive Input Filter w/Attenuation
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CS42432
8.2 DAC Output Filter
The CS42432 is a linear phase design and does not include phase or amplitude compensation for an external filter. Therefore, the DAC system phase and amplitude response will be dependent on the external analog circuitry. Shown below is the recommended active and passive output filters.
1800 pF C0 G 5.49 k 2.94 k 4.75 k 390 pF C0 G
DAC1-3 AOUTx AOUTx +
+
22 F
56 2 47.5 k
1.65 k 5600 pF C0 G
88 7
1200 pF C0 G
1.87 k
2 F 2
Figure 23. Active Analog Output Filter
DAC1-3
3.3 F
AOUTx+
560
+ 10 k C R ext
C=
Rext+ 560 4FSRext 560
Figure 24. Passive Analog Output Filter
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CS42432 9. ADC FILTER PLOTS
Figure 25. SSM Stopband Rejection
Figure 26. SSM Transition Band
0 -1 -2
0.10 0.08 0.06
Amplitude (dB)
-4 -5 -6 -7 -8 -9 -10 0.45
Amplitude (dB)
0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55
-3
0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Frequency (normalized to Fs)
Frequency (normalized to Fs)
Figure 27. SSM Transition Band (Detail)
Figure 28. SSM Passband Ripple
0 -10 -20 -30 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -40
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60
Frequency (normalized to Fs)
Amplitude (dB)
Amplitude (dB)
Frequency (normalized to Fs)
Figure 29. DSM Stopband Rejection
Figure 30. DSM Transition Band
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CS42432
`
0 -1 -2
0 .10 0 .0 8 0 .0 6
Amplitude (dB)
-3 -4 -5 -6 -7 -8
Amplitude (dB)
0 .0 4 0 .0 2 0 .0 0 -0 .0 2 -0 .0 4 -0 .0 6 -0 .0 8
-9 -10 0.46
-0 .10 0 .0 0
0.47 0.48 0.49 0.50 0.51 0.52
0 .0 5
0 .10
0 .15
0 .2 0
0 .2 5
0 .3 0
0 .3 5 0 .4 0
0 .4 5
0 .50
Frequency (normalized to Fs)
Fr e que ncy (norm alize d to Fs )
Figure 31. DSM Transition Band (Detail)
Figure 32. DSM Passband Ripple
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DS673F1
CS42432 10.DAC FILTER PLOTS
Figure 33. SSM Stopband Rejection
Figure 34. SSM Transition Band
0.05
0
-0.05
Amplitude dB
-0. 1
-0.15
-0. 2
-0.25
0
0.05
0.1
0.15
0.2 0.25 0.3 Frequency (normalized to Fs)
0.35
0.4
0.45
0.5
Figure 35. SSM Transition Band (detail)
Figure 36. SSM Passband Ripple
Figure 37. DSM Stopband Rejection
Figure 38. DSM Transition Band
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CS42432
0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0. 1 -0. 2
Amplitude dB
0
0.05
0.1
0.15
0.2 0.25 0.3 Frequency (normalized to Fs)
0.35
0.4
0.45
0.5
Figure 39. DSM Transition Band (detail)
Figure 40. DSM Passband Ripple
0
0
-10
-10
-20
-30
-20
-40 Amplitude (dB)
Amplitude (dB)
0 0.1 0.2 0.3 0.4 0.5 0.6 Frequency(normalized to Fs) 0.7 0.8 0.9 1
-30
-50
-60
-40
-70
-50
-80
-90
-60
-100
0.35 0.4 0.45 0.5 0.55 0.6 Frequency(normalized to Fs) 0.65 0.7 0.75
Figure 41. QSM Stopband Rejection
Figure 42. QSM Transition Band
0
0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 0.4 0.45 0.5 0.55 0.6 Frequency(normalized to Fs) 0.65 0.7
-0. 5
Amplitude dB
Amplitude (dB)
-1
-1. 5
0
0.05
0.1
0.15
0.2 0.25 0.3 Frequency (normalized to Fs)
0.35
0.4
0.45
0.5
Figure 43. QSM Transition Band (detail) 54
Figure 44. QSM Passband Ripple DS673F1
CS42432 11.PARAMETER DEFINITIONS
Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Isolation A measure of crosstalk between the left and right channel pairs. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channel pairs. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.
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CS42432 12.REFERENCES
1. Cirrus Logic, AN18: Layout and Design Rules for Data Converters and Other Mixed Signal Devices, Version 6.0, February 1998. 2. Cirrus Logic, Techniques to Measure and Maximize the Performance of a 120 dB, 96 kHz A/D Converter Integrated Circuit, by Steven Harris, Steven Green and Ka Leung. Presented at the 103rd Convention of the Audio Engineering Society, September 1997. 3. Cirrus Logic, A Stereo 16-bit Delta-Sigma A/D Converter for Digital Audio, by D.R. Welland, B.P. Del Signore, E.J. Swanson, T. Tanaka, K. Hamashita, S. Hara, K. Takasuka. Paper presented at the 85th Convention of the Audio Engineering Society, November 1988. 4. Cirrus Logic, The Effects of Sampling Clock Jitter on Nyquist Sampling Analog-to-Digital Converters, and on Oversampling Delta Sigma ADC's, by Steven Harris. Paper presented at the 87th Convention of the Audio Engineering Society, October 1989. 5. Cirrus Logic, An 18-Bit Dual-Channel Oversampling Delta-Sigma A/D Converter, with 19-Bit Mono Application Example, by Clif Sanchez. Paper presented at the 87th Convention of the Audio Engineering Society, October 1989. 6. Cirrus Logic, How to Achieve Optimum Performance from Delta-Sigma A/D and D/A Converters, by Steven Harris. Presented at the 93rd Convention of the Audio Engineering Society, October 1992. 7. Cirrus Logic, A Fifth-Order Delta-Sigma Modulator with 110 dB Audio Dynamic Range, by I. Fujimori, K. Hamashita and E.J. Swanson. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992. 8. Philips Semiconductor, The IC-Bus Specification: Version 2.1, January 2000. http://www.semiconductors.philips.com
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DS673F1
CS42432 13.PACKAGE INFORMATION 52L MQFP PACKAGE DRAWING
E E1
D D1
1
e
B A A1
L
DIM A A1 B D D1 E E1 e* L
MIN --0.000 0.009 ----------0.029 0.00
INCHES NOM ------0.519 0.394 0.519 0.394 0.026 0.035 4
MAX 0.096 0.010 0.016 ----------0.041 7.00
MIN --0.00 0.22 ----------0.73 0.00
MILLIMETERS NOM ------13.20 BSC 10.00 BSC 13.20 BSC 10.00 BSC 0.65 BSC 0.88 4
MAX 2.45 0.25 0.40 ----------1.03 7.00
* Nominal pin pitch is 0.65 mm Controlling dimension is mm. JEDEC Designation: MS022
13.1
Thermal Characteristics
Parameter Symbol 2 Layer Board 4 Layer Board qJA JA Min Typ 47 38 Max Units C/Watt C/Watt 57
Junction to Ambient Thermal Impedance
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CS42432 14.ORDERING INFORMATION
Product CS42432 Description 4-in, 6-out, TDM CODEC for Surround Sound Apps Package 52L-MQFP Pb-Free YES Container Order # Rail CS42432-CMZ Commercial -10 to +70 C Tape & Reel CS42432-CMZR Rail CS42432-DMZ Automotive -40 to +105 C Tape & Reel CS42432-DMZR CDB42438 Grade Temp Range
CDB42438 CS42432 Evaluation Board
15.REVISION HISTORY
Revision
A1 Initial Release Initial Preliminary Product (PP) Release subject to legal notice below. Added pin numbers to "Typical Connection Diagram (Software Mode)" on page 11 and "Typical Con-
Changes
nection Diagram (Hardware Mode)" on page 12.
Changed ADC Double-Speed Mode parameters. See Note 2 on page 13 and Note 18 on page 21. Changed ADC Passband Ripple maximum specifications for SSM, DSM & QSM in section "Characteristics and Specifications" beginning on page 13. Changed DAC Frequency Response specifications for SSM, DSM & QSM in "Characteristics and Specifications" beginning on page 13. Removed ADC Quad-Speed Mode feature. See Note 19 on page 21. Added section "De-Emphasis Filter" on page 30. Corrected section "TDM data is received most significant bit (MSB) first, on the second rising edge of the SCLK occurring after a an FS rising edge. All data is valid on the rising edge of SCLK. The AIN1 MSB is transmitted early, but is guaranteed valid for a specified time after SCLK rises. All other bits are transmitted on the falling edge of SCLK. Each time slot is 32 bits wide, with the valid data sample left `justified within the time slot. Valid data lengths are 16, 18, 20, or 24." on page 31. Changed AIN1-6 Volume Control range from (+12 dB to -115.5 dB) to (+24 dB to -64 dB) in register "AINX Volume Control (AINX_VOL[7:0])" on page 45. Removed the register "Status Control (address 18h)". See "CLOCK ERROR (CLK ERROR)" on page 46 and "ADC Overflow (ADCX_OVFL)" on page 46 for the Active Mode setting. Corrected Figures 20-22. Added "Ordering Information" on page 58. Updated temperature and voltage specifications in the "Recommended Operating Conditions" on page 13. Added test conditions to the Analog Input and Analog Output Characteristics tables.
PP1
PP2 F1
58
DS673F1
CS42432
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest you, go to www.cirrus.com.
IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. IC is a registered trademark of Philips Semiconductor. SPI is a registered trademark of Motorola, Inc.
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